Anti-fuse for an integrated circuit (IC) product and method of making such an anti-fuse for an IC product
US10892222B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Sep 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative IC product disclosed herein includes a first conductive line positioned at a first level within the IC product and a first conductive structure positioned at a second level within the IC product, wherein the second level is lower than the first level. In this illustrative example, the IC product also includes a second conductive structure that is conductively coupled to the first conductive line, wherein at least a portion of the second conductive structure is positioned at a level that is above the first level and wherein nearest surfaces of the first conductive structure and the second conductive structure are laterally offset from one another by a lateral distance and insulating material positioned between the nearest surfaces of the first conductive structure and the second conductive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.