Removal of a bottom-most nanowire from a nanowire device stack

US10892326B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Patrick H. Keys · Portland, US
• Sean T. Ma · Portland, US
• Stephen M. Cea · Hillsboro, US
• Rishabh Mehandru · Portland, US

Key dates

• Filing date: Mar 30, 2017
• Grant date: Jan 12, 2021
• Expiry date: Mar 30, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.