Low latency synchronization for operation cache and instruction cache fetching and decoding instructions
US10896044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2018 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | Sep 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.