Semiconductor package with in-package compartmental shielding and fabrication method thereof
US10896880B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | Dec 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate. A high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate around the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring to surround the high-frequency chip. A second ground ring is disposed on the top of the substrate around the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring to surround the circuit component. Mold-flow channels are disposed in the first and second metal-post reinforced glue walls. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.