Methods to protect nitride layers during formation of silicon germanium nano-wires in microelectronic workpieces
US10903077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2019 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Jul 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.