Chamferless via structures
US10903118B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 5, 2019 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Jul 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.