Gate-all-around field effect transistors with robust inner spacers and methods

US10903317B1 · kind B1 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Julien Frougier · Albany, US
• Ruilong Xie · Niskayuna, US
• Kangguo Cheng · Schenectady, US
• Chanro Park · Clifton Park, US

Key dates

• Filing date: Aug 7, 2019
• Grant date: Jan 26, 2021
• Expiry date: Aug 7, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/364

Abstract

A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.