Patent · US Active

Semiconductor device and method of manufacturing a semiconductor device using an alignment layer

US10903321B2 · kind B2 · utility

0Cited by

2References

14Claims

0Family size

Assignee

Infineon Technologies Austria AG · AT

Inventors

Martin Poelzl · Ossiach, AT
Oliver Blank · Villach, AT
Franz Hirler · Isen, DE
Maximilian Roesch · Villach, AT
Li Juin Yip · Villach, AT

Key dates

Filing date	Oct 13, 2015
Grant date	Jan 26, 2021
Priority date	—
Expiry date	Dec 18, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/2527
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.