Method of selectively depositing a capping layer structure on a semiconductor device structure
US10910262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of selectively depositing a capping layer structure on a semiconductor device structure is disclosure. The method may include; providing a partially fabricated semiconductor device structure comprising a surface including a metallic interconnect material, a metallic barrier material, and a dielectric material. The method may also include; selectively depositing a first metallic capping layer over the metallic barrier material and over the metallic interconnect material relative to the dielectric material; and selectively depositing a second metallic capping layer over the first metallic capping layer relative to the dielectric material. Semiconductor device structures including a capping layer structure are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.