Package including multiple semiconductor devices
US10910297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Jun 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.