Apparatuses and methods for fuse latch and match circuits
US10916327B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Aug 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure are drawn to apparatuses and methods for fuse latch and match circuits. A memory may include a number of fuse registers, each of which is associated with a line of redundant memory cells. An address may be stored in fuse latches of the fuse register. A dynamic logic circuit may activate one of the fuse registers and a match logic circuit may compare the address stored in the activated fuse register to an address received as part of an access operation to determine if the redundant memory cells should be accessed. The fuse latches may be floated during a power up operation. The dynamic logic circuit may control a timing of the activation and comparison operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.