Memory core chip having TSVS
US10916489B1 · kind B1 · utility
8Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Oct 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06596
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is an apparatus that includes a memory cell army, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.