Self-adaptive termination impedance circuit
US10917093B1 · kind B1 · utility
5Cited by
8References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Nov 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device with a termination circuit providing a termination impedance for a data signal in the memory device. The device also includes a calibration circuit configured to set the termination impedance to a predetermined value. The device further includes an impedance adjustment circuit configured to adjust the termination impedance based on a feedback signal indicating a change in the termination impedance due to at least one of a change in a temperature of the memory device or a change in voltage of a voltage bus in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.