Intellectual property block validation and design integration for integrated circuits
US10922462B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 22, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Nov 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for validating and integrating intellectual property (IP) blocks in integrated circuit design flows for integrated circuits. A method includes unpacking a third-party IP block package to obtain the IP block files, executing an IP block validation rule structure on the IP block files, wherein the IP block validation rule structure is encoded in a tool control language and wherein the IP block validation rule structure includes a plurality of validation tests, each validation test checking a different validity aspect of the IP block files in the IP block package, generating at least one report based on execution of the validation tests to the IP block files, storing successfully validated IP block files in a library, generating a file manifest for the successfully validated IP block files, and providing the file manifest to design tools for designing and manufacturing of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.