SRAM with burst mode operation
US10923185B2 · kind B2 · utility
1Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jun 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.