Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance
US10923435B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 24, 2020 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Feb 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate having at least one semiconductor chip on a top surface of the substrate; a ground ring, on the top surface of the substrate, surrounding the at least one semiconductor chip; a metal-post reinforced glue wall disposed on the ground ring, surrounding the at least one semiconductor chip; a molding compound surrounding the at least one semiconductor chip, wherein a rear surface of the at least one semiconductor chip is flush with an upper surface of the molding compound; a conductive layer disposed on the molding compound and in direct contact with the rear surface of the semiconductor chip and the metal-post reinforced glue wall; a solder layer disposed on the conductive layer; and a heat sink disposed on the solder layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.