Vertical resistor adjacent inactive gate over trench isolation

US10923469B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Hui Zang · Guilderland, US
• Guowei Xu · Lawrence, US
• Jiehui Shu · Clifton Park, US
• Ruilong Xie · Niskayuna, US
• Yurong Wen · Singapore, SG
• Garo Derderian · Boise, US
• Shesh Mani Pandey · Saratoga Springs, US
• Laertis Economikos · Hopewell Junction, US

Key dates

• Filing date: Jan 10, 2019
• Grant date: Feb 16, 2021
• Expiry date: Jan 10, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.