Predictive spatial digital design of experiment for advanced semiconductor process optimization and control
US10929586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2020 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | May 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes methods and systems for building a spatial model to predict performance of processing chamber, and using the spatial model to converge faster to a desired process during the process development phase. Specifically, a machine-learning engine obtains an empirical process model for a given process for a given processing chamber. The empirical process model is calibrated by using the in-line metrology data as reference. A predictive model is built by refining the empirical process model by a machine-learning engine that receives customized metrology data and outputs one or more spatial maps of the wafer for one or more dimensions of interest across the wafer without physically processing any further wafers, i.e. by performing spatial digital design of experiment (Spatial DoE).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.