Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10930341B1 · kind B1 · utility
10Cited by
271References
7Claims
0Family size
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Key dates
| Filing date | Feb 21, 2020 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Feb 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.