Manufacturing process for separating logic and memory array
US10930607B2 · kind B2 · utility
0Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15313
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.