Patent · US Active

Embedded pad structures of three-dimensional memory devices and fabrication methods thereof

US10930661B2 · kind B2 · utility

12Cited by
5References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 17, 2018
Grant dateFeb 23, 2021
Priority date
Expiry dateNov 2, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/35

Abstract

Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The device comprises an array device semiconductor structure comprising an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The device further comprises a peripheral device semiconductor structure comprising a peripheral interconnect layer disposed on a peripheral device and including a second interconnect structure. The device further comprises a pad embedded in the array device semiconductor structure or the peripheral interconnect layer, and a pad opening exposing a surface of the pad. The array interconnect layer is bonded with the peripheral interconnect layer, and the pad is electrically connected with the peripheral device through the first interconnect structure or the second interconnect structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.