Interconnect structure of three-dimensional memory device
US10930663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jul 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts. Each of a conductor layer of the alternating conductor/dielectric stack in the staircase structure, the etch stop layer, and the slit structure is in contact with one of the first contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.