Magnetic memory cell
US10930704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2020 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Mar 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.