Semiconductor package manufacturing method
US10937668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Mar 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package manufacturing method includes the steps of bonding a plurality of semiconductor chips to the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to thereby form a sealing layer from the sealing compound on the front side of the wiring substrate, thereby forming a package substrate, next holding the package substrate on a holding tape, next cutting the front side of the resin layer by using a profile grinding tool to thereby form a plurality of ridges and grooves on the front side of the resin layer, thereby increasing the surface area of the front side of the resin layer, and next dividing the package substrate along each division line to obtain a plurality of individual semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.