Split gate non-volatile memory cells with FinFET structure and HKMG memory and logic gates, and method of making same

US10937794B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Feng Zhou · Ann Arbor, US
• Jinho Kim · Seoul, KR
• Xian Liu · Sunnyvale, US
• Serguei Jourba · Aix-en-Provence, FR
• Catherine Decobert · Saint-Maximin-la-Sainte-Baume, FR
• Nhan Do · Saratoga, US

Key dates

• Filing date: Dec 3, 2018
• Grant date: Mar 2, 2021
• Expiry date: Dec 3, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.