System and method of interfacing co-processors and input/output devices via a main memory system
US10942682B2 · kind B2 · utility
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17References
20Claims
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Key dates
| Filing date | Jul 24, 2020 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Jul 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.