Fast multi-width instruction issue in parallel slice processor
US10942745B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Sep 25, 2018 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Jan 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.