Identifying asynchronous power loss
US10942796B2 · kind B2 · utility
2Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Aug 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/144
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.