Memory device with multiple layers
US10950617B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of word lines spaced from one another in a first direction, a first insulating film provided between adjacent word lines, a plurality of select gates located above the plurality of word lines in the first direction, a first intermediate electrode provided between the plurality of word lines and the select gates, a second insulating film provided between the first intermediate electrode and the select gates, a semiconductor pillar extending through the plurality of word lines, the first insulating film, the first intermediate electrode, the second insulating film, and the select gates, and extending in the first direction, and a charge retention film located between each of the plurality of word lines and the semiconductor pillar, wherein the second insulating film has a second thickness in the first direction that is greater than a first thickness of the first insulating film in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.