Orthogonal transistor layouts
US10950635B2 · kind B2 · utility
0Cited by
2References
14Claims
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Inventors
Key dates
| Filing date | Nov 7, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Nov 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor device includes a plurality of drain fingers that are elongate in a first dimension, a plurality of source fingers that are elongate in the first dimension and interleaved with the plurality of drain fingers, one or more drain contact bars extending over a first set of the plurality of drain fingers and a first set of the plurality of source fingers in a second dimension that is orthogonal to the first dimension, and one or more source contact bars extending over a second set of the plurality of drain fingers and a second set of the plurality of source fingers in the second dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.