Clock circuit and method of operating the same
US10951200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2020 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Feb 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.