Method for stress reduction in semiconductor package via carrier
US10952333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Dec 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices, semiconductor device assemblies, and methods of making such semiconductor devices and semiconductor device assemblies. Material may be removed from a semiconductor device having a first thickness to obtain a second thickness and a carrier may be attached to the semiconductor device having a third thickness with the third thickness plus the second thickness substantially equaling the first thickness. The carrier has a coefficient of thermal expansion (CTE) that differs from the CTE of the semiconductor device. The addition of the carrier to the semiconductor device may change the overall warpage or CTE of a semiconductor device assembly. The semiconductor device assembly be include a redistribution layer between the semiconductor device and a substrate. A material may encapsulate the carrier and the semiconductor device. The carrier may provide electromagnetic shielding. A coating may be applied to external surface of the semiconductor device assembly to provide electromagnetic shielding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.