Retaining cache entries of a processor core during a powered-down state
US10956332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2017 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Nov 11, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.