Semiconductor package metal shadowing checks
US10956649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Aug 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2113/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.