Guided scanning electron microscopy metrology based on wafer topography
US10957608B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Mar 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31798
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about the wafer, which was obtained with the wafer topography measurement system. A metrology sampling plan can be generated for the wafer. This metrology sampling plan can include locations in the wafer topography data above the topography threshold. The scanning electron microscope can scan the wafer using the metrology sampling plan and identify defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.