Asymmetric gate pitch
US10957695B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Oct 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.