Method of reducing charge loss in non-volatile memories

US10957703B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Pawan Singh · Cupertino, US
• Shivananda Shetty · Sunnyvale, US
• James Pak · Sunnyvale, US

Key dates

• Filing date: Aug 6, 2018
• Grant date: Mar 23, 2021
• Expiry date: Sep 13, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.