Patent · US Active

Integrated device comprising memory bitcells comprising shared preload line and shared activation line

US10964380B1 · kind B1 · utility

0Cited by

4References

26Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Zhongze Wang · San Diego, US
Yandong Gao · San Diego, US
Xia Li · San Diego, US
Ye Lu · San Diego, US
Xiaochun Zhu · San Diego, US
Xiaonan Chen · Boise, US

Key dates

Filing date	Feb 6, 2020
Grant date	Mar 30, 2021
Priority date	—
Expiry date	Feb 6, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1437
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.