Selective disabling of hardware-based cache coherency and enforcement of software-based cache coherency
US10970213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, system, and method of enforcing cache coherency in a multiprocessor shared memory system are disclosed. A request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, a hardware-based cache coherency of the system is disabled, and request is processed according to software-based cache coherency protocols and mechanisms. A coherent read request may be translated to a non-coherent request, such as an immediate read request, which does not trigger tracking or storing state and ownership information of the requested memory block, or trigger communications with processors other than those involved with request. Processing a coherent write request may include transmitting an exclusive read request, which is a request for ownership of the memory block identified in the coherent write request, and transmitting a write acknowledgment to the node contro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.