Michael Malewicki
10Patents
1h-index
10Co-inventors
43Inventor score
Filing activity: Apr 10, 2017 → May 11, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10970213B2 | Selective disabling of hardware-based cache coherency and enforcement of software-based cache coherency | Physics | 1 | Active |
| US11714755B2 | System and method for scalable hardware-coherent memory nodes | Physics | 0 | Active |
| US12061552B2 | Application of a default shared state cache coherency protocol | Physics | 0 | Active |
| US10628365B2 | Packet tunneling for multi-node, multi-socket systems | Physics | 0 | Active |
| US10331581B2 | Virtual channel and resource assignment | Physics | 0 | Active |
| US11586541B2 | System and method for scalable hardware-coherent memory nodes | General | 0 | Revoked |
| US11314637B2 | System and method for efficient cache coherency protocol processing | Physics | 0 | Active |
| US10521260B2 | Workload management system and process | Electricity | 0 | Active |
| US11556471B2 | Cache coherency management for multi-category memories | Physics | 0 | Active |
| US11687459B2 | Application of a default shared state cache coherency protocol | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.