Apportionment aware hierarchical timing optimization
US10970455B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2020 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Jan 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.