Sequential error capture during memory test
US10971242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Sep 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.