NAND parity information techniques for systems with limited RAM
US10977115B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 12, 2018 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Dec 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.