Xiangang Luo
107Patents
4h-index
97Co-inventors
71Inventor score
Filing activity: Oct 27, 2004 → Jun 4, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10789126B2 | Multiple memory devices having parity protection | Physics | 7 | Active |
| US10446237B1 | Temperature sensitive NAND programming | Physics | 5 | Active |
| US11314425B2 | Read error recovery | Physics | 4 | Active |
| US11175979B2 | Prioritization of error control operations at a memory sub-system | Physics | 4 | Active |
| US11437108B1 | Voltage bin calibration based on a temporary voltage shift offset | Physics | 2 | Active |
| US11709727B2 | Managing error-handling flows in memory devices | Physics | 2 | Active |
| US10872639B2 | Recovery of memory from asynchronous power loss | Physics | 2 | Active |
| US11409446B2 | Media management on power-up | Physics | 2 | Active |
| US11567682B2 | Temperature management for a memory device using memory trim sets | Physics | 2 | Active |
| US7682755B2 | Lithography mask and optical lithography method using surface plasmon | Physics | 2 | Active |
| US9958784B2 | Super-resolution imaging photolithography | Physics | 2 | Active |
| US10930352B2 | Temperature sensitive NAND programming | Physics | 2 | Active |
| US10747612B2 | Multi-page parity protection with power loss handling | Physics | 2 | Active |
| US11360677B2 | Selective partitioning of sets of pages programmed to memory device | Physics | 2 | Active |
| US11475974B2 | Memory device virtual blocks using half good blocks | Physics | 2 | Active |
| US10915395B2 | Read retry with targeted auto read calibrate | Physics | 2 | Active |
| US11373729B2 | Grown bad block management in a memory sub-system | Physics | 2 | Active |
| US11211100B2 | Recovery of memory from asynchronous power loss | Physics | 1 | Active |
| US12027213B2 | Determining offsets for memory read operations | Physics | 1 | Active |
| US11520491B2 | Parity protection in non-volatile memory | Physics | 1 | Active |
| US11450391B2 | Multi-tier threshold voltage offset bin calibration | Physics | 1 | Active |
| US10977115B2 | NAND parity information techniques for systems with limited RAM | Physics | 1 | Active |
| US11928356B2 | Source address memory managment | Physics | 1 | Active |
| US11776655B2 | Memory device virtual blocks using half good blocks | Physics | 1 | Active |
| US11132044B2 | Dynamic P2L asynchronous power loss mitigation | Emerging Cross-Sectional Technologies | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.