Deterministic test pattern generation for designs with timing exceptions

US10977400B2 · kind B2 · utility

Assignee

• MENTOR GRAPHICS CORPORATION · US

Inventors

• Wu-Tung Cheng · Lake Oswego, US
• Kun-Han Tsai · Lake Oswego, US
• Naixing Wang · Hangzhou City, CN
• Chen Wang · Tigard, US
• Xijiang Lin · West Linn, US
• Mark Kassab · Wilsonville, US
• Irith Pomeranz · West Lafayette, US

Key dates

• Filing date: Aug 22, 2019
• Grant date: Apr 13, 2021
• Expiry date: Aug 22, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.