Patent · US Active

Multi-port high performance memory

US10978143B2 · kind B2 · utility

1Cited by

5References

25Claims

0Family size

Assignee

MARVELL ASIA PTE LTD · SG

Inventors

George M. Braceras · South Burlington, US
Xiaoli Hu · Shanghai, CN
Wei Zhao · Milpitas, US
Igor Arsovski · Williston, US
Yuzheng Jin · Shanghai, CN
Hao Pu · Shanghai, CN
Shuangdi Zhao · Shanghai, CN
Qing Li · Beijing, CN

Key dates

Filing date	Aug 26, 2019
Grant date	Apr 13, 2021
Priority date	—
Expiry date	Aug 26, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.