Multi integrated circuit chip carrier package
US10978314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Oct 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.