Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
US10978427B2 · kind B2 · utility
31Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Oct 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.