Semiconductor device with bit lines at different levels and method for fabricating the same
US10978459B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Sep 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate and a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction; an air gap disposed between the first bit line contact and the second bit line contact; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts. The top surfaces of the plurality of second bit line contacts and the top surfaces of the plurality of first bit lines are positioned at different levels along a second direction substantially perpendicular to the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.