Power semiconductor device with dV/dt controllability and low gate charge

US10978560B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Alexander Philippou · Munich, DE
• Roman Baburske · Otterfing, DE
• Christian Jaeger · Munich, DE
• Johannes Georg Laven · Taufkirchen, DE
• Helmut Maeckel · Munich, DE

Key dates

• Filing date: Mar 28, 2019
• Grant date: Apr 13, 2021
• Expiry date: Mar 28, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

A power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.